The present invention relates to a semiconductor device including at least first and second insulated gate transistors integrated on a single substrate and a method for manufacturing the same and, more specifically, to a semiconductor device with a MIS structure such as a DRAM (dynamic random access memory) including both a memory cell section and its peripheral circuit section mounted on one chip and a method for manufacturing. the same.
To miniaturize and highly integrate a plurality of insulated gate transistors on a semiconductor substrate is generally useful for achieving high performance of an LSI since the area of devices occupied on the substrate is decreased, the current driving power of the devices is increased, the parasitic capacitance thereof is reduced, and so on. A trial product of a CMOS whose gate length is typically 0.1 xcexcm or less has been already successful at research level, and its high performance has been indeed confirmed.
A serious hindrance to the miniaturization is a short-channel effect in which the absolute value of a threshold voltage drops as the gate length decreases. To prevent this, a so-called scaling rule is proposed, and a transistor is decreased in size according thereto, with the result that the impurity concentration of the substrate has to be increased, or the thickness of an insulation film has to be decreased and so has to be the junction depth of a source/drain region (impurity diffusion layer). In particular, the decrease in the junction depth becomes more important as a solution for suppressing the short-channel effect.
On the other hand, the depth of the impurity diffusion layer need to be great to some extent at a point away from a channel in order to mitigate the parasitic resistance of the insulated gate transistor using the salicide technique. In other words, if silicide is formed on the source/drain region, the junction leakage current between the impurity diffusion layer and substrate becomes large. This large leakage current is prevented by forming an impurity diffusion layer having a considerable depth.
A source/drain extension structure is proposed with a view to suppressing the short-channel effect. In this structure, ion implantation for forming a shallow junction is performed to form a so-called extension region of source/drain. A side-wall (gate side-wall) is formed on the side-wall portion of a gate electrode and then ion implantation is carried out to form an impurity diffusion layer having a sufficiently deep junction except where the gate side-wall is formed. That is, the impurity diffusion layer is formed at a position away from the end portion of the extension region having a shallow junction, by the length of the gate side-wall.
A gate side-wall forming process is employed for obtaining the extension structure. Conventionally, the same gate side-wall length is used for all transistors constituting an LSI. Therefore, particularly in a DRAM including a memory cell section and its peripheral circuit section on one chip, the gate side-wall lengths of a transistor with a small channel width used in the memory section and a transistor with a large channel width used in the peripheral circuit section are not matching each other. This is due to the fact that the design rule of the transistor of the peripheral circuit section is close to an isolation pattern, whereas the memory cell section employs a pattern reduced to the limitation of the lithography technique.
For example, an SAC (self-aligned contact) technique using an etching rate difference of a silicon nitride film to a silicon oxide film provided on the gate side-wall, is generally used when a contact hole is formed in the source/drain region of the memory cell section. If, however, the gate side-wall length is not scaled down in accordance with the design rule (scaling rule), no gate side-wall can be formed in the memory cell section. It is therefore difficult to form a contact hole using the SAC technique and thus impossible to form a memory cell section.
As described above, it is necessary to reduce the gate side-wall length according to the scaling rule in the transistor of the memory cell section. On the other hand, when the gate side-wall length is scaled down, an inconvenience occurs in the transistor of the peripheral circuit section.
As has been described, in particular, when silicide is formed on the impurity diffusion layer of the transistor, the junction depth of the impurity diffusion layer has to be sufficiently large in order to decrease the junction leakage current due to the formation of the silicide. If the gate side-wall length is small, impurities are greatly diffused in the horizontal (lateral) direction under the gate side-wall, which seriously influence on the short-channel effect. Therefore, in order to improve the current drive while suppressing the short-channel effect in the transistor of the peripheral circuit section, the gate side-wall length is greatly increased and the resistance of the impurity diffusion layer has to be considerably small.
As described above, the conventional semiconductor device has a drawback wherein the requirements of both a transistor whose gate side-wall need to be reduced in length according to the scaling rule and a transistor whose gate side-wall need to be increased in length considerably and whose impurity diffusion layer need to be decreased in resistance sufficiently, cannot be satisfied at the same time.
It is accordingly an object of the present invention to provide a semiconductor device capable of improving in packed density and performance by integrating, on the same substrate, both a first insulated gate transistor which allows a fine contact hole to be formed so as to be self-aligned with a gate electrode and a second insulated gate transistor which sufficiently mitigates the parasitic resistance while suppressing the short-channel effect.
To attain the above object, according to a first aspect of the present invention, there is provided a semiconductor device of a MIS structure including at least first and second transistors integrated on a semiconductor substrate, wherein a side-wall length of a second side-wall insulation film formed on a side-wall portion of a second gate electrode of the second transistor is greater than a side-wall length of a first side-wall insulation film formed on a side-wall portion of a first gate electrode of the first transistor.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region;
a plurality of first transistors integrated in the memory cell region of the semiconductor substrate and having first gate electrodes, a first side-wall insulation film being formed on a side-wall portion of each of the first gate electrodes by a first insulator; and
at least one second transistor provided in the peripheral circuit region of the semiconductor substrate and having a second gate electrode, a second side-wall insulation film being formed on a side-wall portion of the second gate electrode by both the first insulator and a second insulator.
According to a third aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region;
a plurality of first transistors integrated in the memory cell region of the semiconductor substrate and having first gate electrodes, a first side-wall insulation film being formed on a side-wall portion of each of the first gate electrodes by a first insulator;
at least one second transistor provided in the peripheral circuit region of the semiconductor substrate and having a second gate electrode, a second side-wall insulation film being formed on a side-wall portion of the second gate electrode by both the first insulator and a second insulator; and
a third insulator provided between the first insulator and the second insulator so as to cover a surface of the semiconductor substrate.
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
a plurality of first transistors formed in a memory cell region on a semiconductor substrate and including first gate electrodes each of which is provided with a first side-wall insulation film formed of a first insulator having a length of approximately d, a maximum space between the first gate electrodes being smaller than 2(d+x); and
a plurality of second transistors formed in a peripheral circuit region on the semiconductor substrate and including both second gate electrodes each of which is provided with a second side-wall insulation film formed of at least the first insulator having a length of approximately d and low-resistance regions each provided on a surface of a diffusion region located away from the first insulator by a distance of approximately x, a maximum space between the second gate electrodes being larger than 2(d+x).
According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming first gate electrodes of a plurality of first transistors, which constitute a memory cell section, in a memory cell region on a semiconductor substrate and forming a second gate electrode of at least one second transistor, which constitutes a peripheral circuit section, in a peripheral circuit region on the semiconductor substrate;
forming a first side-wall insulation film of a first insulator on a side-wall portion of each of the first gate electrodes; and
forming a second side-wall insulation film on a side-wall portion of the second gate electrode by both the first insulator and a second insulator.
According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming a field region by which an element region is divided into a memory cell region and a peripheral circuit region;
forming first gate electrodes of a plurality of first transistors, which constitute a memory cell section, in the memory cell region, and forming a second gate electrode of at least one second transistor, which constitutes a peripheral circuit section, in the peripheral circuit region;
depositing a first insulative material above an entire surface of the semiconductor substrate;
selectively removing the first insulative material to form both a first side-wall insulation film of a first insulator on a side-wall portion of each of the first gate electrodes and the first insulator on a side-wall portion of the second gate electrode;
depositing a second insulative material above the entire surface of the semiconductor substrate; and
selectively removing the second insulative material to form a second side-wall insulation film of the first insulator and a second insulator on a side-wall portion of the second gate electrode.
According to a seventh embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming first gate electrodes of a plurality of first transistors, which constitute a memory cell section, in a memory cell region on a semiconductor substrate and forming a second gate electrode of at least one second transistor, which constitutes a peripheral circuit section, in a peripheral circuit region on the semiconductor substrate;
depositing a first insulative material above an entire surface of the semiconductor substrate;
selectively removing the first insulative material to form a first insulator on each of side-portions of the first gate electrodes and the second gate electrode;
depositing a second insulative material above the entire surface of the semiconductor substrate; and
selectively removing the second insulative material to leave the second insulative material between the first gate electrodes.
In the semiconductor device according to the present invention and the method for manufacturing the same, the side-wall insulation film of the gate electrode in the second insulated gate transistor can be increased considerably, while that of the gate electrode in the first insulated gate transistor is scaled down in accordance with the scaling rule. It is thus possible to simultaneously satisfy the requirements of both a transistor which necessitates reducing the length of the side-wall insulation film in accordance with the scaling rule and another transistor which necessitates sufficiently increasing the length of the side-wall insulation film and considerably decreasing the resistance of the impurity diffusion layer.
According to the present invention, if a space between the gate electrodes of the first and second insulated gate transistors is defined, a patterned low-resistance region can be formed selectively on the surface of the diffusion layer but not through the lithographic process.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.